CKS=others, RPSS=00, TOPS=00, RPES=00
WDT Control Register
| TOPS | Timeout Period Selection 0 (00): 1,024 cycles (03FFh) 1 (01): 4,096 cycles (0FFFh) 2 (10): 8,192 cycles (1FFFh) 3 (11): 16,384 cycles (3FFFh) |
| Reserved | These bits are read as 00. The write value should be 00. |
| CKS | Clock Division Ratio Selection 0 (others): setting prohibited 1 (0001): PCLK/4 4 (0100): PCLK/64 6 (0110): PCLK/512 7 (0111): PCLK/2048 8 (1000): PCLK/8192 15 (1111): PCLK/128 |
| RPES | Window End Position Selection 0 (00): 75 percent 1 (01): 50 percent 2 (10): 25 percent 3 (11): 0 percent (window end position is not specified) |
| Reserved | These bits are read as 00. The write value should be 00. |
| RPSS | Window Start Position Selection 0 (00): 25 percent 1 (01): 50 percent 2 (10): 75 percent 3 (11): 100 percent (window start position is not specified) |
| Reserved | These bits are read as 00. The write value should be 00. |